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Modular multiplication is one of the most critical finite field operation for hardware implementations of asymmetric cryptography. Hyper-threaded modular multipliers are proposed for FPGA implementations based on a small number DSP blocks/slices. A code generator (VHDL) allows the exploration of various parameters such as the size of field elements, algorithms, optimizations, architecture parameters. Both code generator and a set of predefined results (multipliers units) are provided.

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