Modular multiplication is one of the most critical finite field operation for hardware implementations of asymmetric cryptography. Hyper-threaded modular multipliers are proposed for FPGA implementations based on a small number DSP blocks/slices. A code generator (VHDL) allows the exploration of various parameters such as the size of field elements, algorithms, optimizations, architecture parameters. Both code generator and a set of predefined results (multipliers units) are provided.

Etablishment : C.N.R.S. - Délégation régionale Bretagne et Pays de la Loire

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• Development Status : 5 - Production/Stable
• Environment : Console (Text Based)
• Intended Audience : Developers
• License : CeCILL : CeCILL-B
• Operating System : POSIX : GNU/Linux
• Programming Language : Python
• Programming Language : Unix Shell
• Topic : Scientific/Engineering : Electronic Design Automation (EDA)

Registered: 2018-02-23 07:28
Activity Ranking: 68
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