Lab 02: Create a minimal SoC with LiTeX

Objectives

  1. Create a minimal SoC from scratch

  2. See how to instantiate different CPU cores

Prerequisites

Firstly we will configure the environnement for the lab.

LiteX installation and setup has been done in a Python virtual environment, so activate it:

source venv/pyenv-litex/bin/activate

To generate the software you need a software toolchain. For LiteX to use the toolchain you have to configure it:

export PATH="INSTALL-PATH/riscv64-unknown-elf-gcc-8.3.0-2019.08.0-x86_64-linux-ubuntu14/bin:$PATH"

All the materials for the lab are available in the following folder:

cd hands-on/lab02

Discover a minimal SoC for simulation

The folder contains a file called lab02-litex-sim.py. It describes a minimal SoC which target a simulation platform.

You can test it by doing

make soc_sim_gateware
make soc_sim_demo
make soc_sim_demo_run

Build a SoC and change the CPU

Change the CPU used by using a picorv32. To use this cpu you need to install the pythondata-cpu-picorv32 if not available in the third_party folder. To do that observe the Makefile and change the cpu-type option.

At the end of the process you should have something like that

        __   _ __      _  __
       / /  (_) /____ | |/_/
      / /__/ / __/ -_)>  <
     /____/_/\__/\__/_/|_|
   Build your hardware, easily!

 (c) Copyright 2012-2022 Enjoy-Digital
 (c) Copyright 2007-2015 M-Labs

 BIOS built on Dec  6 2022 01:26:43
 BIOS CRC passed (99b0f0ac)

 LiteX git sha1: a4cc859d

--=============== SoC ==================--
CPU:            PicoRV32 @ 1MHz
BUS:            WISHBONE 32-bit @ 4GiB
CSR:            32-bit data
ROM:            128KiB
SRAM:           8KiB
MAIN-RAM:       64KiB

--========== Initialization ============--

--============== Boot ==================--
Booting from serial...

You can observe that the CPU has changed.

Take aways